The redundancy technique (fault relieving technique) is extensively used as a useful means to increase the yield and to reduce the manufacturing cost of semiconductor memories. It is a method by which a small number each of redundant word lines and redundant bit lines are provided in advance to substitute for any faulty word lines and faulty bit lines, respectively, that may be found. To store the addresses of faulty word lines and faulty bit lines, a programmable element (fuses are used usually), into which faulty addresses detected by inspection are to be registered, is provided on the chip. In accessing the memory, the demanded address and the registered faulty address are compared and, if they are founded identical, a reserve word line or a reserve bit line is selected or, if not, the regular word line or the regular bit line is selected.
In a hierarchical word line system in which word lines comprise main word lines and sub-word lines, a plurality of sub-word lines are allocated for each main word line. For the selection of one sub-word line out of the plurality of sub-word lines allocated for one main word line, a sub-word line selection line is provided. For this reason, there is some allowance in the wiring pitch of the main word lines on the memory array, and it is conceivable to arrange the sub-word line selection line or a power supply line by utilizing the wiring layer in which the main word lines are formed. However, if a short circuiting fault arises between the main word lines, sub-word line selection line and power supply line, short circuiting between the main word lines could be relieved by replacing them with reserve main word lines. However, if a short circuiting fault occurs on the sub-word line selection line or the power supply line, it will constitute a D.C. fault or a function fault, which is irrelievable, and therefore the chip itself will become faulty.
Therefore, an object of the present invention is to provide a semiconductor integrated circuit device which is made less susceptible to faults while seeking a higher level of integration in a simple structure. This and other objects and novel features of the invention will become apparent from the description in this specification and drawings appended hereto.